FIG. 1 shows a communications network 10. The communications network 10 is a telephone network. While the invention is illustrated herein using a telephone network, it is equally applicable to other communication networks such as cable television networks, data networks, etc. The communications network 10 includes one or more private branch exchanges (PBX's) 21, one or more end central offices 22, and one or more toll central offices 23 which are interconnected via trunk links 31, 32. The PBX 21 may be at a customer's premises. The PBX 21 illustratively provides for local voice and data communications at the customer premises. The PBX 21 also provides access to the trunks 31 for purposes of enabling communications to other customer premises via the central office 22 and central office 23.
Illustratively, communications is achieved by transmitting a digital signal in the form of a bitstream on the trunks 31 and 32. The PBX 21 converts analog signals transmitted thereon into digital signals. These signals are then multiplexed according to a time division multiplexing scheme into a higher rate signal such as a DS1 signal. The higher rate signals are received at the central office 22. The central office 22 may demultiplex selected lower rate digital signals therefrom for transmission to their respective destination customer premises. The central office 22 may also multiplex selected ones of the higher rate signals received from the trunks 31 into an even higher rate signal, such as a DS2 signal.
Illustratively, at least the higher rate signal into which the lower rate signals are multiplexed, is organized according to a frame structure. FIG. 2 illustrates a frame structure for a DS2 signal. Illustratively, the DS2 signal is organized into master frames 50 with 1,176 bits which master frames comprise four subframes 51, 52, 53 and 54 with 294 bits each. Each subframe 51-54 is assigned to a channel and each channel may be assigned for carrying the data of a corresponding lower rate signal. Each subframe 51, 52, 53 or 54 comprises a series of six groups of forty-nine bits 51-1, 51-2, 51-3, 51-4, 51-5 and 51-6, or 52-1, 52-2, 52-3, 52-4, 52-5 and 52-6, or 53-1, 53-2, 53-3, 53-4, 53-5 and 53-6, or 54-1, 54-2, 54-3, 54-4, 54-5 and 54-6. Each of the groups begins with a control bit labeled M, C, F or X. The bits M.sub.0, M.sub.1, F.sub.0 and F.sub.1 are framing bits used to synchronize a receiver to the frames of the signal. The bit X is an alarm bit. The bits C.sub.1, C.sub.2, C.sub.3, and C.sub.4 are stuffing control bits for the channels 1, 2, 3 and 4, respectively. Their purpose is explained below.
Each of the first five groups 51-1 to 51-5, 52-1 to 52-5, 53-1 to 53-5 and 54-1 to 54-5 of each subframe 51-54 also includes forty-eight payload bits for carrying data of a lower rate signal. The last group 51-6, 52-6, 53-6 and 54-6 of each subframe 51-54 includes forty-seven payload bits and one stuffing bit S.sub.1, S.sub.2, S.sub.3 or S.sub.4. The stuffing bits S.sub.1, S.sub.2, S.sub.3 or S.sub.4 may carry either a data bit or a null bit; therefore, the subframes 51-54 may carry two hundred eight-seven or two hundred eighty-eight data bits of the corresponding channel. The purpose of the stuffing bits may be better explained with reference to FIG. 3.
Consider that in multiplexing plural lower rate signals into a higher rate signal, each lower rate signal must be synchronous with the higher rate signal. However, the incoming lower rate signals are likely to be mutually asynchronous with each other. Even if all lower rate signals were generated in synchronism with a single clock, each signal is subject to clock instabilities such as noise and interference, changes in the length of the transmission media (the trunk lines 32, 31), changes in the velocity of propagation of the lower rate signals on the transmission media, doppler shifts and irregular timing information. Such clock instabilities are discussed in greater detail in J. BELLAMY, DIGITAL TELEPHONY, ch. 7, p. 333-360 (1991) which is incorporated herein by reference. Therefore, each of the incoming lower rate signals is first synchronized to the higher rate signal before it is multiplexed therein. FIG. 3 shows an illustrative synchronizer 60 and desynchronizer 70 which may be used for preliminarily synchronizing and multiplexing plural lower rate signals into a higher rate signal and for demultiplexing and regenerating the constituent lower rate signals from the higher rate signal. Illustratively, the synchronizer 60 may be present at the central office switch 22 and the desynchronizer 70 may be present at the central office switch 23. The synchronizer and desynchronizer could therefore be connected together by a trunk line 32.
The synchronizer 60 is provided with an elastic store or buffer 620 for synchronizing an incoming lower rate signal to the higher rate signal. A write clock is illustratively generated by the write clock recovery circuit 610 from incoming payload data of a lower rate signal. The write clock also causes a write pointer counter 615 to increment the write pointer stored therein with each clock pulse. The write pointer is outputted by the write pointer counter 615 to a write address input of the elastic buffer 620 so as to point to each address of the elastic buffer 620 successively. The write clock is furthermore inputted to a write clock input of the elastic buffer 620 so as to enable the elastic buffer 60 to store the next incoming bit. Thus, incoming payload data bits of the lower rate signal are stored in successive addresses of the elastic buffer 620 in synchronism with the write clock.
A local oscillator 640 is provided for generating a read clock for reading out the bits from the elastic buffer 620. For reasons discussed below, the read clock is inputted to the read clock input of the elastic buffer 620 via a logical circuit 645. The logic circuit 645 outputs a "gapped" read clock (which "gapped" read clock is described in greater detail below) to a read pointer counter 625. The gapped read clock causes the read pointer counter 625 to increment a read pointer stored therein with each gapped read clock pulse. The read pointer is outputted by the read pointer counter 625 to a read address input of the elastic buffer 620. Thus, data bits are read out of successive addresses of the elastic buffer in synchronism with the gapped read clock signal outputted from the logical circuit 645.
The provision of the elastic buffer 620 tends to reduce the instabilities in the low rate signal. However, the write clock of at least one of the lower rate signals to be multiplexed is not precisely synchronous with the read clock (of the higher rate signal). Instead, the read and write clocks are nearly synchronous or plesiochronous. If the read clock is faster than the write clock, an underflow may occur in the elastic buffer 620. If the read clock is slower than the write clock, an overflow may occur in the elastic buffer 620. If either an underflow or overflow occurs, a discontinuity is introduced into the low rate signal data that is multiplexed into the high rate signal. Such a discontinuity is referred to as a "slip."
It is desirable to prevent slips from occurring. To prevent the likelihood of both overflow and underflow, a "pulse-stuffing" technique is utilized in the multiplexer 60. According to the pulse-stuffing technique in DS1 to DS2 mapping, the data rate of the channel into which the lower rate signal is multiplexed is purposely made slightly higher than the lower rate signal. The channel has payload bit positions for carrying the data bits of the lower rate signal and stuffing bits, i.e., S.sub.1, S.sub.2, S.sub.3 and S.sub.4 for channels 1, 2, 3 and 4, respectively. The stuffing bits can carry either a data bit or a null bit. At times when the write clock is running faster than the read clock, it may be necessary to read out extra bits to prevent an overflow. The extra read-out bits are inserted into the stuffing bit positions. At other times, the stuffing bits carry a null value. The stuffing control bits C.sub.1, C.sub.2, C.sub.3 and C.sub.4 are used in their respective subframes 51, 52, 53 or 54 to indicate whether or not the stuffing bit carries a data bit or a null bit. In the DS2 frame, if all of the C.sub.1 bits in the subframe 51 are set to logic `1`, the stuffing bit S.sub.1 carries a data bit. Otherwise, the stuffing bit S.sub.1 carries a null bit.
As shown, the write pointer outputted from the write pointer counter 615 and the read pointer outputted from the read pointer counter 625 are inputted to a comparison circuit 630. The comparison circuit 630 forms the phase difference between the write pointer and the read pointer. Illustratively, this is illustrated in FIG. 4(a). As shown, the phase difference is of the form of a sawtooth wave with a varying amplitude. Note that the use of the write pointer and read pointer for forming the phase difference is a matter of convenience. Alternatively, the write clock and gapped read clock could be used although additional processing may be necessary to produce the phase difference between these two signals.
The phase difference thus formed is outputted to a justification decision circuit 635. The justification decision circuit illustratively compares the phase difference signal outputted by the comparison circuit 630 to a threshold as shown in FIG. 4(b). In response to this comparison, the justification decision circuit 635 outputs a justification signal which comprises plural pulses, including one pulse corresponding to each instance in which the phase difference signal exceeds the threshold. The outputted justification signal is shown in FIG. 4(c). (Illustratively, the signals of FIGS. 4(a)-(c) are exaggerated for purposes of illustrating the invention.) As shown, the pulses of the justification signal have a pulse width equal to the interval during which the phase difference exceeds the threshold.
The justification signal outputted by the justification circuit 635 is inputted as one input to the logic circuit 645 which may be a logic AND gate. As noted above, the logic circuit 645 also receives the read clock generated by the local oscillator 640. Furthermore, the logic circuit 645 may receive a frame timing signal from the multiplexer 650 such as is shown in FIG. 4(d). The frame timing signal is high during payload and stuffing bit positions of the channel of the higher rate signal corresponding to the lower rate signal and is low at other times. The justification signal and frame timing signals act as enable signals for enabling the pulses of the read clock to be outputted to from the logic circuit 645. As a result, the logic circuit 645 outputs a gapped read clock signal such as is shown in FIG. 4(e). As shown, the gapped read clock signal is not a smooth and continuous clock signal. Rather, the gapped read clock signal is irregular, containing pulses separated by regularly occurring gaps for control bits and irregularly occurring gaps for stuffing bits. Such gaps introduce waiting time jitter into the data signal. Herein, "jitter" means the short term variation of significant instants of a signal from their ideal positions in time. FIG 5(a) shows an un-jittered waveform and FIG. 5(b) shows the same waveform with jitter. FIG. 5(c) is a plot of jitter versus time. The ordinate or amplitude is the amount of phase shift .theta.(t) measured in unit intervals or u.i. of time, wherein one u.i is equal to one period of the signal. Via a Fast Fourier Transform (FFT), the spectral plot of jitter in the frequency domain can be obtained. Generally speaking, waiting time jitter has an amplitude that depends on the normalized stuff-ratio .rho. which is given by: ##EQU1## where: f.sub.w is the write clock frequency
f.sub.r is the read clock frequency, and PA1 F is the frame rate of the higher rate signal
In any event, the average rate of the gapped read clock over a long period of time is approximately the same as the data rate of the incoming data of the lower rate signal. Therefore, the likelihood of slips is dramatically reduced or eliminated. The data read out of the elastic buffer 620 in synchronism with the gapped read clock is multiplexed with other like signals by the data pump 650 to produce a higher rate signal. As discussed above, each channel of the higher rate signal has extra stuffing bits for storing a null bit or a data bit. The data bits read out in synchronism with the gapped read clock are placed in the payload bit positions and the stuffing bit positions of the corresponding channel. The higher rate signal is then transmitted to the desynchronizer 70.
The higher rate signal received by the desynchronizer 70 is first inputted to a data pump 750 which demultiplexes the data of each lower rate signal. In demultiplexing the higher rate signal, it is necessary to generate a clock for the demultiplexed data of each lower rate signal. Because, the data of the lower rate signals are transferred as synchronous data, the derived clock must be continuous. The generation of such a continuous clock is complicated by the insertion of the overhead control bits (e.g., the M, X, F and C bits). However, the overhead bits occur in a predetermined fashion and can be easily removed. The waiting time jitter which occurs because of the predictable overhead bits M, F, C, and X can be removed using an elastic store 720 and a read clock derived from the higher rate signal. Like the synchronizer 60, the desynchronizer 70 includes a write pointer counter 715 and a read pointer counter 725 which perform similar functions as the write pointer counter 615 and read pointer counter 625 in the synchronizer circuit 60.
On the other hand, the waiting time jitter introduced by the pulse-stuffing is significantly more difficult to remove. This is because the gaps produced by the data carrying and null stuffing bits are irregular and unpredictable. Therefore, the clock for the data of the lower rate signal must be generated from the average arrival rate of each channel's data and not from the higher rate signal. To that end, a phase-locked loop (PLL) circuit 760 is provided. The PLL circuit 760 has a voltage controlled oscillator (VCO) 765 which generates a read clock. The read clock generated by the VCO 765 causes the read pointer counter 725 to increment and is inputted to the read clock input of the elastic buffer 720. The read clock generated by the VCO is also inputted to a phase detector of the PLL 760. The phase difference detector 770 also receives the write clock which is generated by the data pump 750 from the higher rate signal. (The write clock also causes the write pointer counter 715 to increment and is inputted to the write clock input of the elastic buffer 720). The phase difference detector circuit 770 outputs, amongst other things, a signal corresponding to the phase difference of the read clock and the write clock. (Illustratively, the phase difference detector multiplies the read clock signal and the write clock signal. This produces a harmonic which corresponds to the difference between the phase of the read clock and the write clock, as well as other higher frequency harmonics.) The signal outputted by the phase difference detector circuit 770 is low pass filtered in the low pass filter (LPF) 775. (This signal may be low pass filtered by one or more than one low pass filters to remove the undesired harmonics of the signal outputted by the phase difference detector circuit 770.) The low-pass filtered phase difference is then fed as a control input to the VCO 765 to adjust the read clock generated therefrom. The net result is that a relatively smooth and continuous read clock is produced from the irregular, gapped write clock with approximately the average rate as the write clock.
The data read out of the elastic buffer 720 and the smoothed read clock are inputted to a line interface 780. The line interface 780 illustratively regenerates the lower rate signal from the smoothed read clock and the read-out data. The line interface 780 may include a LPF 785 to further smooth the read clock.
The synchronizer 60 and desynchronizer 70 enable communications which removes most of the waiting time jitter. However, the waiting time jitter introduced by pulse-stuffing can have frequency components down to 0 Hz. This is illustrated in FIG. 4(f) which shows the justification signal produced by the justification decision circuit 635 superimposed on the phase difference signal produced by the phase comparison circuit 630. The justification signal corresponds to a (relatively) high frequency waiting time jitter component. However, the envelope of the phase difference signal corresponds to a (relatively) low frequency waiting time jitter component. Even with a relatively large elastic buffer 720 and slowly adjusted read clock, some low frequency jitter will always be present.
Waiting time jitter produced by pulse-stuffing has been studied in the prior art. See D. Duttweiler, Waiting Time Jitter, BELL SYS. TECH. J., vol. 51, pp. 165-207, January, 1972; P. E. K. Chow, Jitter Due to Pulse Stuffing Synchronization, IEEE TRANS. COMM., vol. COM-21, pp. 854-859, July, 1973; W. Grover, T. Moore & J. McEachern, Waiting Time Jitter Reduction by Synchronizer Stuff Threshold Modulation, PROC. OF GLOBECOMM, pp. 13.7.1-13.7.5 (1987); G. Pierbon & R. Valussi, Jitter Analysis of a Double Modulated Threshold Pulse Stuffing Synchronizer, IEEE TRANS. COMM., vol. 39, no. 4, pp. 594-602, April, 1991. Of these prior art references, the article W. Grover, T. Moore & J. McEachern, Waiting Time Jitter Reduction by Synchronizer Stuff Threshold Modulation, PROC. OF GLOBECOMM, pp. 13.7.1-13.7.5 (1987) suggests a novel approach to removing low frequency waiting time jitter. This article proposes a stuff threshold modulation (STM) technique wherein the low frequency jitter is "modulated," i.e., changed, to a higher frequency. Such a higher frequency jitter is then easily removed by a conventional PLL circuit 760 (FIG. 3) in the desynchronizer 70. To that end, this article proposes to use a sawtooth threshold signal, such as shown in FIG. 4(g), rather than a fixed threshold, in the justification decision circuit 635 (FIG. 3). That is, the phase difference produced by the pointer comparison circuit 630 (FIG. 3) at each instant is compared to a sawtooth waveform threshold at the corresponding instant in the justification decision circuit 635, as shown in FIG. 4(h). The justification decision circuit 635, in turn, generates a pulse having a pulse width that equals the period during which the phase difference exceeds the sawtooth threshold as shown in FIG. 4(i). The net result is that overflow and underflow are still avoided in the elastic buffer 620 of the synchronizer 60 but the waiting time jitter produced by the pulse-stuffing is modulated to a higher frequency. The PLL circuit 760 of the desynchronizer 70 then filters out the high frequency waiting time jitter, including the part of the low frequency jitter which is modulated to a higher frequency. As a result, less residual low frequency waiting time jitter is present in the recovered clock.
The STM technique reduces the amount of waiting time jitter. However, the level of the waiting time jitter is still unacceptably high for some applications.
It is therefore an object of the present invention to overcome the disadvantages of the prior art.